Shift register and disp1ay apparatus using same

专利摘要:
According to the present invention, a driver circuit is used for an image display device of a TFT active matrix type, which is integrally formed on a display panel, and a start pulse SP having an amplitude lower than a drive voltage is input, which is stepped up to a start pulse SPO by a level shifter. In a shift register configured to be input to the flip-flop F1 of the shift register section, when the first-stage flip-flop F1 outputs the output signal S1, the level shifter is deactivated, and the last-stage flip-flop Fn outputs the output signal Sn. A motion control circuit for activating the level shifter is provided. Thus, it is possible to reduce the power consumption of the level shifter between the start pulse SPO being transmitted from flip-flop F2 to flip-flop Fn-l.
公开号:KR20030077427A
申请号:KR10-2003-0018417
申请日:2003-03-25
公开日:2003-10-01
发明作者:마츠다에이지；교우텐세이지로；와시오하지메
申请人:샤프 가부시키가이샤；
IPC主号:

专利说明:

SHIFT REGISTER AND DISP1AY APPARATUS USING SAME}
[24] BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a shift register which is preferably used for a driving circuit of a liquid crystal display device and operates in response to an input signal of a relatively low voltage, and a display device such as a liquid crystal display device using the same.
[25] In the scan signal line driver circuit and the data signal line driver circuit of the liquid crystal display device, a shift register is widely used to create a scan signal provided to each scan signal line or to take a timing to sample each data signal from a video signal. Thus, the scan signal line driver circuit and the data signal line driver circuit using the shift register are disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-322020 (published: November 24, 2000, corresponding US Patent Application No. 09 / 568,889), Japanese Laid-Open Patent Publication No. 2000-339984 (published: December 8, 2000, corresponding US application: 09 / 578,440), Japanese Laid-Open Patent Publication No. 200l-307495 (published: January 2, 2001) , US Application No. 09 / 703,9l8).
[26] On the other hand, the power consumption of the electronic circuit increases in proportion to the square of frequency, load capacity and voltage. Therefore, in the circuit connected to the liquid crystal display device, such as a circuit for generating a video signal to the liquid crystal display device, or the liquid crystal display device itself, the driving voltage tends to be gradually set to reduce the power consumption. .
[27] However, in circuits formed of polycrystalline silicon thin film transistors in order to ensure a large display area, such as pixel circuits, scan signal line driver circuits, and data signal line driver circuits, the threshold voltages vary even between substrates or within the same substrate. In some cases, the driving voltage includes a margin so as to absorb the influence of the threshold voltage difference, and it is difficult to say that the driving voltage is sufficiently reduced. On the other hand, like the video signal generating circuit, the driving voltage in a circuit using a single crystal silicon transistor is often set to, for example, 5 [V], 3.3 [V] or less.
[28] Therefore, a start pulse lower than the drive voltage of the shift register is applied to the display panel from an external circuit such as the video signal generating circuit. In this case, the shift register is provided with a level shifter for boosting the start pulse. Specifically, for example, as shown in the shift register 1 in Fig. 12, the level shifter 3 is provided on the input side of the shift register section 2, and the 5 [V] from the video signal generation circuit is provided. The start pulse SP of the precision amplitude is boosted to a start pulse SPO of, for example, about 15 [V], which is the driving voltage of the shift register section 2, and is the first stage flip-flop F1 in the shift register section 2. It is configured to enter.
[29] The flip-flop f1 at the first stage transfers the start pulse SPO after boosting to the flip-flop f2 after the step-up in synchronization with the clock signal CK from the video signal generating circuit. This operation is performed sequentially in the flip-flops f1, f2, ..., fn-1, fn connected in series with each other, and the flip-flops f1, f2, ..., fn-1, fn of each stage are performed sequentially. From the output signals s1, s2, ..., sn-1, sn, selection pulses are sequentially output.
[30] 13 is a block diagram showing an example of the configuration of the level shifter 3. The level shifter 3 includes a pair of NMOS transistors n1 and n2, PMOS transistors p1 and p2, and two stages of inverters lnv1 and inv2. The gates of the NMOS transistors n1 and n2 are connected to each other, the drain is connected to the drains of the PMOS transistors p1 and p2, respectively, the source of the NMOS transistor n1 is grounded, and the gate and the drain of the NMOS transistor n1 are connected, and the NMOS is connected. The start pulse SP is input to the source of the transistor n2. The sources of the PMOS transistors p1 and p2 are commonly given a high level driving voltage Vcc of about 15 [V], and the gates are grounded together.
[31] Therefore, the start pulse SP input to the source of the NMOS transistor n2 is boosted to the drive voltage Vcc and output from the output terminal which is the connection point of the drain of the PMOS transistor p2 and the drain of the NMOS transistor n2. The output is amplified by two stages of inverters inv1 and inv2, and is output as the start pulse SPO after the step-up at the electrostatic output.
[32] In the level shifter 3 configured as described above, the NMOS transistors n1 and n2 and the PMOS transistors p1 and p2 constitute a current-driven level shift unit, regardless of whether or not the start pulse SP is input. The PMOS transistors p1 and p2 are always in the ON state. Therefore, the gates of the NMOS transistors n1 and n2 are at a high level, and current flows in the NMOS transistors n1 and n2 also in the ON state. Therefore, even if the amplitude of the start pulse SP is lower than the threshold voltage of the NMOS transistor n2, the start pulse SP can be boosted without any problem.
[33] On the other hand, in the voltage drive type level shifter in which the input switching element is turned on / off by the level of the input signal, the step-up operation cannot be performed when the amplitude of the start pulse SP is lower than the threshold voltage of the input switching element. However, the current-driven level shifter has a problem that power consumption is large because current flows as described above.
[34] SUMMARY OF THE INVENTION An object of the present invention is to provide a shift register capable of operating normally by a level shifter and reducing power consumption in the level shifter even when the input signal is made small in order to reduce power consumption. It is to provide a display device used.
[1] Fig. 1 is a block diagram showing the electrical configuration of a shift register as a first embodiment according to the present invention.
[2] FIG. 2 is a block diagram showing in detail an example of the configuration of a shift register section in the shift register shown in FIG.
[3] 3 is a waveform diagram for explaining the operation of the shift register.
[4] FIG. 4 is a block diagram showing an example of the configuration of an operation control circuit in the shift register shown in FIG.
[5] Fig. 5 is a block diagram showing an example of the configuration of a current drive type level shifter according to the present invention.
[6] Fig. 6 is a block diagram showing an example of the configuration of an image display apparatus to which a shift register according to the present invention is applied.
[7] FIG. 7 is an equivalent circuit diagram of pixels in the image display device shown in FIG.
[8] 8 is a block diagram showing an electrical configuration of a shift register of another embodiment according to the present invention.
[9] FIG. 9 is a block diagram showing an example of the configuration of an input control circuit and a level shift unit in the shift register shown in FIG.
[10] Fig. 10 is a block diagram showing an electrical configuration of a shift register of still another embodiment according to the present invention.
[11] FIG. 11 is a block diagram showing an example of the configuration of an output stabilization circuit, an input control circuit, and a level shift section in the shift register shown in FIG.
[12] 12 is a block diagram of a typical prior art shift register.
[13] FIG. 13 is a block diagram showing an example of a configuration of a level shifter in the shift register shown in FIG.
[14] Fig. 14 is a block diagram showing the electrical configuration of a shift register of another embodiment according to the present invention.
[15] FIG. 15 is a block diagram showing the shift register section in detail in the shift register shown in FIG.
[16] FIG. 16 is a block diagram showing an example of the configuration of an analog switch in the shift register section shown in FIG.
[17] FIG. 17 is a waveform diagram for explaining the operation of the shift register shown in FIG.
[18] FIG. 18 is a block diagram showing an example of a configuration of an operation control circuit in the shift register shown in FIG.
[19] Fig. 19 is a block diagram showing an electrical configuration of a shift register of still another embodiment according to the present invention.
[20] 20 is a block diagram showing in detail an example of a configuration of a shift register section in the shift register shown in FIG.
[21] FIG. 21 is a waveform diagram for explaining the operation of the shift register shown in FIG.
[22] Fig. 22 is a block diagram showing the electrical configuration of the shift register of yet another embodiment according to the present invention.
[23] Fig. 23 is a block diagram showing an electrical configuration of a shift register of another embodiment according to the present invention.
[35] The shift register of the present invention is a shift register for sequentially transmitting a signal in which a plurality of stages of flip-flops are input, stepping up the input signal having an amplitude lower than a driving voltage of the flip-flop, thereby providing a flip-flop at the first stage. In response to the output of the level shifter applied to the flip-flop of any x-th stage and the flip-flop of any y-th stage (where x <y), the x-th stage flip-flop And a motion control circuit for disabling the level shifter when transmitting a signal, and activating the level shifter when the flip-flop of the y-th stage transmits the input signal.
[36] According to the above arrangement, in a shift register in which a plurality of flip-flops are sequentially transmitted in synchronization with a clock signal, an input signal such as a start pulse, the amplitude shifter being lower in amplitude than the drive voltage of the flip-flop. In response to the input signal being boosted and input, the operation control circuit disables the level shifter when the x-th stage flip-flop transmits the input signal, and the y-th stage flip-flop receives the input signal. When transmitting, it is activated. That is, the level shifter is deactivated while the input signal is transmitted from the remaining x th stage to the flip-flop of the y th stage, and the next input signal period from the y th stage where the input signal is likely to be input to the level shifter. The level shifter is activated only for the period up to the x th stage of the.
[37] Therefore, even if the input signal is made small in order to reduce power consumption, the input signal can operate normally and the power consumption of the level shifter during the period transmitted from the x th to the y th stage can be reduced. have.
[38] In the shift register of the present invention, it is preferable that the x-th stage is the first stage and the y-th stage is the last stage.
[39] According to the above configuration, y-x, i.e., the period during which the level shifter is inactive, becomes the maximum value, and the power consumption can be reduced the most.
[40] Furthermore, the shift register of the present invention is a shift register capable of sequentially transmitting signals inputted by a plurality of flip-flops and switching a shift direction, the amplitude of which is lower than the driving voltage of the flip-flop. A level shifter that boosts the input signal and applies it to a flip-flop of any s-th stage, and a flip-flop of any x-th stage (where s ≤ x) and any y-th stage (where x In response to the output of the flip-flop of <y), the level shifter is deactivated when the flip-flop of the x-th stage transmits the input signal, and the flip-flop of the y-th stage transmits the input signal. And an operation control circuit for activating the level shifter.
[41] According to the above arrangement, in the so-called bidirectional shift register which is capable of transferring the input signals such as start pulses and the plurality of flip-flops sequentially in synchronization with the clock signal and switching the shift direction, In response to boosting and inputting the input signal having an amplitude lower than the driving voltage of the flip-flop, the operation control circuit deactivates the level shifter when the flip-flop of the x-th stage transmits the input signal, and y The flip-flop of the first stage is activated when the input signal is transmitted. That is, the level shifter is deactivated while the input signal is being transmitted from the remaining xth stage to the flip-flop of the yth stage, and the next input from the yth stage where the input signal is likely to be input to the level shifter. The level shifter is activated only for the period up to the xth end of the period of the signal.
[42] Here, the input signal is input to a flip-flop at any s-th stage (where s ≤ x), so that the output from the flip-flop after the s-th stage is valid. That is, for example, when the output from these flip-flops is used for image display, after the sth stage becomes the effective display area. When the shift direction is switched, the flip-flops that were the first stage to the s-1 stage are the last stage to the last stage (s-2) stage to perform the shift operation.
[43] Therefore, even if the input signal is made small in order to reduce the power consumption, the input signal can operate normally and the power consumption of the level shifter in the period shifted from the x th to the y th stage can be reduced. have.
[44] In the shift register of the present invention, it is preferable that the x-th stage is the s-th stage and the y-th stage is the last stage.
[45] According to the above arrangement, the period y-x, that is, the period during which the level shifter is inactive is maximized, and the power consumption can be reduced the most. Further, for example, in the case of being used for the image display, the last stage to the last stage (s-2) stage are outside the effective display area, but these flip-flops function as a dummy, thereby making the effective After the selection of the display area is finished, the level shifter can be activated at an arbitrary timing.
[46] Further, in the shift register of the present invention, it is preferable that the level shifter has a current driving level shift portion which is always connected to an input switching element provided with the input signal during operation.
[47] According to the above configuration, unlike the voltage-driven level shifter in which the input switching element conducts / blocks by the level of the input signal, the current switching level shifter is always connected during operation. Therefore, even when the amplitude of the input signal is lower than the threshold voltage of the input switching element, the input signal can be boosted without any problem.
[48] On the other hand, as described above, the current-driven level shifter consumes more power than the voltage-driven level shifter because the input switching element is conductive during operation, but the input signal is controlled by the operation control circuit. When is inputted, the operation of the level shifter is stopped to suppress the power consumption, and the present invention can be particularly preferably applied.
[49] In addition, the shift register of the present invention, when the operation control circuit deactivates the level shifter in relation to the operation control circuit, causes the input switching element to block the input of the input switching element of the level shift unit. It is preferable to further include an input control circuit for providing a level signal.
[50] According to the above configuration, a case where the input switching element is a MOS transistor, for example, will be described with respect to the current-driven level shifter to which the input switching element is conducting during operation as described above. In the configuration applied to the input control circuit, the input switching element can be cut off when the level control signal between the drain and the source is applied to the gate. In the configuration in which the input signal is applied as a source, the input control circuit cuts off the input switching element, for example, by applying a signal having a potential substantially the same as the drain to the source.
[51] In this way, the deactivation of the current-driven level shifter can be realized, the through current of the input switching element can be reduced during deactivation, and a shift resistor with lower power consumption can be realized.
[52] Further, in the shift register of the present invention, it is preferable that the level shifter includes an output stabilization circuit which maintains an output voltage at a predetermined value in the case of the deactivation.
[53] According to the above configuration, if the output voltage of the level shifter becomes negative while the level shifter is stopped, the operation of the flip-flop connected to the level shifter may become unstable. By maintaining the output voltage of the level shifter at a predetermined value, the malfunction of the flip-flop due to the negative output voltage can be prevented and a more stable shift register can be realized.
[54] In addition, in the display device of the present invention, a scan signal line driver circuit and a data signal line driver circuit are provided in each pixel area formed by a plurality of scan signal lines and data signal lines that cross each other. In a display device configured to display by writing a signal, at least one of the scanning signal line driver circuit and the data signal line driver circuit is formed integrally with the display panel and has the shift register.
[55] According to the above configuration, each pixel region is formed by being divided by a plurality of intersecting scan signal lines and data signal lines, and a driving circuit for sequentially selecting the scan signal lines or data signal lines is formed integrally on the display panel. In a matrix display device of a driver monolithic type, any one of the shift registers is mounted on at least one of a scan signal line driver circuit and a data signal line driver circuit which are integrally formed.
[56] Therefore, the integrally formed drive circuit formed of polycrystalline silicon has a high operating voltage and low drive voltage of the external circuit, due to its low mobility and the like, compared to an external circuit formed of a single crystal silicon chip. Since the level shifter needs to be mounted in the drive circuit to which the signal from the external circuit is input, the shift register of the present invention can be applied.
[57] In this way, the driver monolithic display panel with low power consumption can be realized.
[58] Other objects, features, and superiority of the present invention will be fully understood by the following detailed description. Further advantages of the present invention will become more apparent from the following description with reference to the accompanying drawings.
[59] A first embodiment according to the present invention will be described with reference to FIGS. 1 to 7 as follows.
[60] Fig. 1 is a block diagram showing the electrical configuration of the shift register 11 of the first embodiment according to the present invention. In this shift register 11, a level shifter 13 is provided on the input side of the shift register section 12, and a start pulse SP having an amplitude of about 5 [V] from the video signal generating circuit is supplied to the shift register section ( It is configured to boost to a start pulse SPO of, for example, about 15 [V], which is the driving voltage Vcc of 12), and to input it to the first flip-flop F1 in the shift register section 12.
[61] The shift register section 12 is input from the video signal generating circuit and, although not shown, is disclosed, for example, in Japanese Unexamined Patent Publication No. 2000-339984 (published: December 8, 2000). And n-stage flip-flops F1, F2, ..., Fn-1, Fn operating at the drive voltage Vcc in synchronization with the clock signal CK boosted by the level shifter. The flip-flop F1 at the first stage transfers the start pulse SPO after boosting to the flip-flop F2 at cutoff in synchronization with the clock signal CK. This operation is performed sequentially at the next flip-flops F2, F3, ..., Fn-1, Fn, which are connected in series with each other, so that from each stage flip-flops F1, F2, ..., Fn-1, Fn As the output signals S1, S2, ..., Sn-1, Sn, selection pulses are sequentially output.
[62] It should be noted that in this shift register 11, the level shifter 13 is deactivated in response to the transfer output of the start pulse SPO from the flip-flop F1 at the first stage, and the flip-flop Fn at the final stage. And an operation control circuit 14 for outputting an enable signal ENB for activating the level shifter 13 in response to the transmission output of the start pulse SPO at.
[63] 2 is a block diagram showing an example of the configuration of the shift register unit 12 in detail. In this example, the flip-flops F1 to Fn are constituted by a set reset flip-flop (SR flip-flop). The clock signal CK input from the outside is directly given to the clock input terminal CK of the flip-flops F1, F3, ..., Fn-1 of odd-numbered stages. The clock signal CK is inverted from the inverter INV and then provided to the clock input terminals CK of the flip-flops F2, F4, ..., Fn of even-numbered stages.
[64] The start pulse SPO after the step-up is input to the set terminal S of the flip-flop F1 at the first stage, the output signal S1 is output at the output terminal Q of the flip-flop F1, and the set terminal S of the flip-flop F2 of the cutoff. do. The output signal S2 is output from the output terminal Q of the flip-flop F2, and is input to the set terminal S of the flip-flop F3 (not shown) of the cutoff, and to the reset terminal R of the flip-flop F1 of the front end. Thereafter, in the same manner, the output signals S3 to Sn-1 are output at the output terminals Q of the flip-flops F3 to Fn-1, respectively, and are input to the set terminals S of the flip-flops F4 to Fn of the cutoff, Is input to the reset terminal R of the flip-flops F2 to Fn-2. At the output terminal Q of the flip-flop Fn, the output signal Sn is output, input to the reset terminal R of the flip-flop Fn-1 at the front end, and to the reset terminal R of the terminal.
[65] Therefore, as shown in Fig. 3, the flip-flop F1 is set at the rising timing of the clock signal CK with the start pulse SP being active at a high level, and each subsequent flip-flop F2 to Fn is It is set for every half period of the clock signal CK, and the start pulse SP is sequentially transmitted. Each flip-flop F1 to Fn-1 is reset to its output when the blocking flip-flops F2 to Fn are set, and the flip-flop Fn at the final stage is immediately after outputting the set output of the rosewood. Is reset to the set output of the rosewood.
[66] As the output of the shift register 11 configured as described above, the output signals S1 to Sn-1 are valid. However, as described above, for the operation control of the level shifter 13 by the operation control circuit 14 described later, The output signal Sn of the last stage is used. In this case, as shown in Fig. 3, the enable signal ENB becomes inactive at a high level when the output signal S1 at the first stage is output, and at a low level when the output signal Sn at the final stage is output. It becomes active.
[67] 4 is a block diagram showing an example of the configuration of the operation control circuit 14. This operation control circuit 14 is composed of a set reset flip-flop (SR flip-flop) composed of two inverted logic circuits NORl and NOR2 having a CMOS configuration. The output signal S1 of the first stage flip-flop F1 is input to one input of one inversion logic circuit NOR1, and the output signal Sn of the flip-flop Fn of the last stage is input to one input of the other inversion logic circuit NOR2. Is entered. To the other inputs of the inversion logic circuits NORl and NOR2, the outputs of the other inversion logic circuits NOR2 and NOR1 are respectively input.
[68] Therefore, the enable signal ENB, which is the output of the inversion logic circuit NOR2, as described above, at the time when the output signal S1 is output, the output of the inversion logic circuit NOR1, that is, the other input of the inversion logic circuit NOR2 is brought to a low level. Since the output signal Sn is at the low level, it is set at the inactive high level. Thereafter, even when the output signal S1 goes low, the output of the inversion logic circuit NOR1 is kept at low level, and the output of the inversion logic circuit NOR2 is kept at high level by the high level output of the inversion logic circuit NOR2. The enable signal ENB remains set at the high level.
[69] On the other hand, when the output signal Sn is outputted, the enable signal ENB, which is the output of the inversion logic circuit NOR2, is reset to the active low level, whereby the two inputs of the inversion logic circuit NOR1 are brought low together, thereby inverting the inversion. The output of the logic sum circuit NOR1 goes high. Thereafter, even when the output signal Sn is at a low level, the output of the inversion logic circuit NOR2 is self-holding at a low level by the high level output of the inversion logic circuit NOR1, and the enable signal ENB is again output signal. It remains set at the low level until S1 is output.
[70] The level shifter 13 is constituted by the current drive type level shifter shown in Fig. 5 so that the voltage can be stepped up without problems even when the start pulse SP has a low amplitude. 5 is a block diagram showing an example of the configuration of the level shifter 13. The level shifter 13 includes a pair of NMOS transistors n1 and n2, PMOS transistors p1 and p2, and two stages of inverters INV1 and INV2. The gates of the NMOS transistors n1 and n2 are connected to each other, the drain is connected to the drains of the PMOS transistors p1 and p2, respectively, the source of the NMOS transistor n1 is grounded, the gate and the drain of the NMOS transistor n1 are connected, and the NMOS transistor is connected. The start pulse SP is input to the source of N2, and the high-level driving voltage Vcc of about 15 [V] is commonly provided to the sources of the PMOS transistors p1 and p2. Same as the shifter 3.
[71] At the output terminal, which is a connection point between the drain of the PMOS transistor P2 and the drain of the NMOS transistor N2, the start pulse SP input to the source of the NMOS transistor N2 is boosted to the driving voltage Vcc and output. This output is amplified by two stages of inverters INV1 and lNV2, and is output as the start pulse SPO after the step-up at the electrostatic output.
[72] Therefore, when the amplitude of the start pulse SP is lower than the threshold voltage of the input switching element, the voltage cannot be operated as a voltage shift type level shifter in which the input switching element conducts / blocks according to the level of the input signal. When the input switching element (NMOS transistor N2) to which an input signal is provided is used as the current-driven level shifter which always conducts, the start pulse SP can be boosted without any problem and the transistor characteristics are low. It is also applicable to cases where high speed drive is required.
[73] However, in this level shifter 13, the enable signal ENB is commonly provided to the gates of the PMOS transistors P1 and P2 different from the level shifter 3 shown in FIG. Therefore, in the current-driven level shift section 13a consisting of the NMOS transistors n1 and n2 and the PMOS transistors p1 and p2, the PMOS transistors p1 and p2 are turned ON only during a low level period in which the enable signal ENB is activated. State, the gates of the NMOS transistors n1 and n2 are at a high level, and the NMOS transistors n1 and n2 are also turned on, so that a current flows. In this way, the power consumption of the current-driven level shifter 13 with large power consumption can be reduced.
[74] In the above description, the operation control circuit 14 deactivates the level shifter 13 in response to the output signal S1 from the flip-flop F1 at the first stage, and outputs the output signal Sn at the flip-flop Fn at the final stage. In response, the level shifter 13 is activated, but the level shifter 13 is deactivated in response to the output signal Sx at the flip-flop Fx of any x-th stage, and the y-th stage (where x < The level shifter 13 may be activated in response to the output signal Sy at the flip-flop Fy of y). However, as described above, by setting x = first stage and y = final stage, the period during which y-x, i.e., the level shifter 13 is inactive, is at a maximum, and power consumption can be reduced the most.
[75] The shift register 11 configured as described above is widely applicable to a shift register whose amplitude of the input signal is lower than the driving voltage. However, as a preferred use example, the shift register 11 will be described in the case where it is applied to an image display apparatus. 6 is a block diagram of the image display device 21. As shown in FIG. This image display device 21 is configured such that a control circuit 23 for generating a video signal DAT is mounted on the display panel 22 approximately. The display panel 22 includes a display unit 24 having pixels PIX arranged in a matrix length, a scan signal line driver circuit 25 and a data signal line driver circuit 26 for driving the pixels P1X. . The scan signal line driver circuit 25 is composed of a shift register 25a, and the data signal line driver circuit 26 is composed of a shift register 26a and a sampling circuit 26b, and these shift registers 25a and 26a. In at least one of the above, the shift register 11 is applied.
[76] The display section 24 and both drive circuits 25 and 26 are monolithically formed on the same substrate in order to reduce the time during manufacture and the wiring capacitance. In addition, in order to integrate more pixels P1X and to enlarge the display area, the display section 24 and the driving circuits 25 and 26 are made of a polycrystalline silicon thin film transistor or the like formed on a glass substrate. In addition, even when a conventional glass substrate having a distortion point of 600 ° C. or lower is used, the polycrystalline silicon thin film transistor is manufactured at a process temperature of 600 ° C. or lower so that distortion or bending due to a process above the distortion point does not occur.
[77] The display section 24 includes the scan signal line driver circuit 25 and the data signal line in a region of each pixel PIX formed by being divided by m scan signal lines GL1 to GLm and k data signal lines DL1 to DLk that cross each other. The drive circuit 26 displays the image by sequentially writing the video signal DAT from the control circuit 23 through the scan signal lines GL1 to GLm and the data signal lines DL1 to DLk. Each pixel PIX is configured as shown in FIG. 7, for example. In Fig. 7, along with the scanning signal line GL and the data signal line DL, an arbitrary integer i below k and an arbitrary integer j below m are added to the pixel PIX indicating an address.
[78] Each pixel PIX includes a field effect transistor (switching element) SW whose gate is a scan signal line GL, whose source is connected to the data signal line DL, and a pixel capacitor Cp whose one electrode is connected to the drain of the field effect transistor SW. It is composed. The other electrode of the pixel capacitor Cp is connected to a common electrode line common to the telephone station P1X. The pixel capacitor Cp is composed of a liquid crystal capacitor CL and a storage capacitor Cs added as necessary.
[79] Therefore, when the scan signal line GL is selected, the field effect transistor SW is turned on, and the voltage applied to the data signal line DL is applied to the pixel capacitor Cp. On the other hand, while the selection period of the scan signal line GL ends and the field effect transistor SW is cut off, the pixel capacitor Cp keeps the voltage at the cutoff. Here, the transmittance or reflectance of the liquid crystal changes with the voltage applied to the liquid crystal capacitor CL. Therefore, by selecting the scan signal line GL and applying a voltage corresponding to the video signal DAT to the data signal line DL, the display state of the pixel PIX can be changed in accordance with the video signal DAT.
[80] Here, between the control circuit 23 and the data signal line driver circuit 26, the video signal DAT to each pixel PIX is transmitted in time division, and the data signal line driver circuit 26 has a clock of a predetermined cycle which becomes a timing signal. At the timing based on the signal CKS and the start pulse SPS, video data to each pixel PIX is extracted from the video signal DAT. Specifically, the shift register 26a sequentially shifts the start pulse SPS in synchronization with the clock signal CKS from the control circuit 23, thereby generating output signals D1 to Dk having different timing at predetermined intervals, and sampling. The circuit 26b samples the video signal DAT at the timing indicated by the respective output signals D1 to Dk, and outputs the data signal lines DL1 to DLk.
[81] In this manner, in the scan signal line driver circuit 25, the shift register 25a sequentially shifts the start pulse SPG in synchronization with the clock signal CKG from the control circuit 23, thereby scanning with different timing at predetermined intervals. The signal is output to each scan signal line GL1 to GLm.
[82] In the image display apparatus 21 configured as described above, the display portion 24 and the driving circuits 25 and 26 formed on the display panel 22 are formed of a polycrystalline silicon thin film transistor or the like as described above. The drive voltage Vcc is set to, for example, about 15 [V], whereas the control circuit 23 formed of a separate integrated circuit chip is formed of a single crystal silicon transistor, and the drive voltage thereof is, for example, It is set to a value lower than the drive voltage Vcc of 5 [V] or less.
[83] In this way, the display section 24, the driver circuits 25, 26 and the control circuit 23 are formed on different substrates, but the number of signals transmitted between them is the display section 24 and the driver circuit. It is much less than the number of signals between 25 and 26, and is about the video signal DAT, each start pulse SPS, SPG and each clock CKS, CKG. In addition, since the control circuit 23 is formed of a single crystal silicon transistor, it is easy to ensure sufficient driving capability. Therefore, even if formed on different substrates, an increase in time, wiring capacity, or power consumption at the time of manufacture is suppressed to the extent that it does not become a problem.
[84] In this way, the drive circuits 25 and 26 formed in the monolithic type on the display panel 22 are formed of polycrystalline silicon or the like, and start pulses are applied to the level shifter 13 required by the drive voltage being higher than the external circuit. By activating only during the period in which the SP is input, a display panel with low power consumption can be realized.
[85] Another embodiment of the present invention will be described with reference to FIGS. 8 and 9 as follows.
[86] 8 is a block diagram showing the electrical configuration of the shift register 31 of another embodiment according to the present invention. The shift register 31 is similar to the shift register 11, and the same reference numerals are given to the parts corresponding to each other, and description thereof will be omitted. It should be noted that in the shift register 31, when the operation control circuit 14 deactivates the level shifter 13 in response to the enable signal ENB, the shift of the level shifter 13a is performed. In the input of the input switching element, the input control circuit 32 is provided with a signal of a level at which the input switching element blocks.
[87] 9 is a block diagram showing an example of the configuration of the input control circuit 32 and the level shift section 13a. The input control circuit 32 is composed of an NMOS transistor N3 provided between the gate and the source of the NMOS transistors N1 and N2, and the gate is provided with the enable signal ENB.
[88] Therefore, when the enable signal ENB is at an active low level, the NMOS transistor N3 is turned off, and the level shift section 13a operates. In contrast, when the enable signal ENB is at an inactive high level, the NMOS transistor N3 is turned on, and the ground state is provided to the gates of the NMOS transistors N1 and N2, thereby turning off the NMOS transistors N1 and N2. The operation of the level shift section 13a can be stopped.
[89] That is, in the case where the NMOS transistor N3 is not provided, even when the enable signal ENB becomes inactive high level and the PMOS transistors P1 and P2 are turned off, the drain potentials of the MOS transistors P1 and N1 and the NMOS transistor N1 And while the gate potential of N2 is in an unstable state, by providing the NMOS transistor N3, the drain potentials of the MOS transistors P1 and N1 and the gate potentials of the NMOS transistors N1 and N2 are set to the ground level, and the NMOS transistors N1 and N2 can be reliably turned off.
[90] When the level shifter 13 stops operating, the voltage output by the input control circuit 32 may be a voltage other than the input dynamic range of the level shifter 13, but as described above, the level shifter 13 In the case of the current driving type, setting the NMOS transistor N2, which is an input switching element, to an OFF state, that is, a voltage at which no through current flows, can reduce power consumption due to the through current, and therefore, lower the power consumption. The shift register which is the power consumption can be realized.
[91] In this way, the deactivation of the current-driven level shifter 13 can be realized, and the current of the NMOS transistor N2 serving as the input switching element can be reduced.
[92] Another embodiment according to the present invention will be described with reference to FIGS. 10 and 11 as follows.
[93] Fig. 10 is a block diagram showing the electrical configuration of the shift register 41 of still another embodiment according to the present invention. The shift register 41 is similar to the shift register 31, and the same reference numerals are given to corresponding parts, and the description thereof is omitted. It should be noted that in this shift register 41, when the operation control circuit 14 deactivates the level shifter 13 in response to the enable signal ENB, the shift of the level shifter 13a. It is provided with the output stabilization circuit 42 which keeps an output voltage at a predetermined value.
[94] Fig. 11 is a block diagram showing an example of the configuration of the output stabilization circuit 42, the input control circuit 32 and the level shift section 13a. The output stabilization circuit 42 is composed of an NMOS transistor N4, the gate of which is provided with the enable signal ENB, the source is grounded, and the drain is connected to the output of the level shift section 13a, and thus to the input of the inverter INV1. Connected.
[95] Therefore, when the enable signal ENB becomes the active low level, the NMOS transistor N4 is turned off, and the start pulse SPO boosted by the level shifter 3 is output. On the other hand, when the enable signal ENB becomes the inactive high level, the NMOS transistor N4 is turned on, and the input of the inverter INV1 is set to the ground level. In this way, while the level shifter 13 is stopped, the output voltage of the level shifter 13 can be maintained at a predetermined value, thereby preventing malfunction of the flip-flop F1. It can be realized.
[96] Another embodiment of the present invention will be described with reference to FIGS. 14 to 18 as follows.
[97] Fig. 14 is a block diagram showing the electrical configuration of the shift register 51 of another embodiment according to the present invention. In the shift register 51, portions corresponding to the shift registers 11 are denoted by the same reference numerals, and description thereof will be omitted. It should be noted that this shift register 51 has a shift register section 52 composed of a bidirectional shift register. The shift register section 52 is composed of n-stage flip-flop circuits H1, H2, ..., Hn-1, Hn.
[98] However, in this shift register section 52, the shift direction can be switched in response to the switching signal LR, and outputs the selection pulses in the order of the output signals S2, ..., Sn-1, Sn as described later. In the forward direction, when the switching signal LR is at the high level, it is shifted in the forward direction. When the switching signal LR is at the low level, the output signals Sn-1, Sn-2, ..., S2, S1 Outputs the selection pulse in the reverse direction. The switching signal LR is configured like the level shifter 13 in a low amplitude signal of about 5 [V] produced by the control circuit 23 or the like of the image display device 21, like the start pulse SP. The level shifter 53 is stepped up by the switching signal LRO having an amplitude of about 15 [V], and is then commonly input to the flip-flop circuits H1 to Hn.
[99] Here, in such a shift register section 52, the first flip-flop circuit H1 and the last flip-flop circuit Hn are dummy, and the corresponding data signal lines DL1, DLn are connected to the image display device 21 or the like. Is formed outside the effective display area and does not contribute to the display. However, as will be described later, these flip-flop circuits H1 and Hn have an operation of resetting the flip-flop circuits of the previous stages in the bidirectional shift operation. Specifically, when the switching signal LR is at the high level, since the shift in the forward direction, the flip-flop circuit Hn becomes the final stage of the shift operation, and outputs the flip-flop circuit Hn-1 of the preceding stage. Reset. On the other hand, when the switching signal LR is at the low level, since the shift in the reverse direction, the flip-flop circuit H1 becomes the final stage of the shift operation, and the output of the flip-flop circuit H2 is reset by the output. do. As described above, the flip-flop circuits H1 and Hn are dummy, and their outputs are not used as an effective display area of the image display device 21, but in order to activate the level shifter 13. You can use it. In other words, as will be described later, these flip-flop circuits H1 and Hn may be made to activate the level shifter 13 after the selection of the effective display area is completed. For this reason, in the shift register section 52 composed of n-stage flip-flop circuits of H1 to Hn, the dummy flip-flop circuit is arbitrarily in response to the timing of activating the level shifter 13. It is set.
[100] However, since the same dummy is required even in the reverse scanning, except for the dummy flip-flop circuit provided on the ultra-short side, the flip-flop circuit to which the start pulse SPO is inputted is the s-th stage (this shift register portion ( In the case of 52), a flip-flop circuit for deactivating the level shifter 13 with Hs of s = 2 is set to Hx (x = 2 in the shift register section 52) of the x-th stage. It needs to be s ≤ x. In addition, when the flip-flop circuit for activating the level shifter 13 is set to Hy in the y-th stage (y = n in the shift register section 52), it is necessary that x <y. Preferably, as described above, by setting x = s and y = n, the period in which the sth stage to the last nth stage, that is, the level shifter 13 is deactivated is maximized, and the power consumption is most reduced. You can.
[101] 15 is a block diagram showing the shift register section 52 in detail. The flip-flop circuits H1 to Hn have a basic configuration of the flip-flop F1 to Fn, and a pair of analog switches AS1 to ASn and BS1 to BSn with respect to the set terminal S in order to realize the bidirectional shift operation. (As a general term, denoted by reference numerals AS and BS.), And a pair of flip-flop circuit analog switches AR1 to ARn and BR1 to BRn for the reset terminal R. Reference numerals AR and BR). In addition, the inverter INV1r is provided to the analog switches BS and BR to provide the switching signal LROB inverting the switching signal LRO.
[102] For the set terminal S of the flip-flop F1, the analog switch AS1 is turned on when the switching signal LRO is at a high level, and grounds the set terminal S, and is turned off when at a low level. The analog switch BS1 is turned OFF when the switching signal LRO is high level, and is turned ON when the switching signal LRO is high level, and connects the set terminal S to the output terminal Q of the flip-flop F2 of the cutoff.
[103] In addition, with respect to the reset terminal R of the flip-flop F1, the analog switch AR1 is turned on when the switching signal LRO is at a high level to provide a high level driving voltage Vcc to the reset terminal R, and to low. Level, the signal is turned off. On the other hand, the analog switch BR1 is turned off when the switching signal LRO is at a high level, and is turned on when the switching signal LRO is at a low level. It provides and resets.
[104] With respect to the set terminal S of the flip-flop F2 of the interruption, the analog switch AS2 is turned on when the switching signal LRO is at a high level, and provides the start pulse SPO to the set terminal S, and is turned off when at a low level. On the contrary, the analog switch BS2 is turned off when the switching signal LRO is at high level, and is turned on when the switching signal LRO is at high level, and the set terminal S is connected to the output terminal Q of the flip-flop F3 of the cutoff. Connect.
[105] In addition, with respect to the reset terminal R of the flip-flop F2, the analog switch AR2 is turned ON when the switching signal LRO is at a high level, and the output terminal Q of the flip-flop F3 of the blocking flip-flop F3 is turned off to the reset terminal R. Output is supplied, and when it is at the low level, the signal is turned off. On the other hand, the analog switch BR2 is turned off when the switching signal LRO is at a high level, and is turned on when the switching signal LRO is at a high level. R is provided with the output at the output terminal Q of the flip-flop F1 of the front end and reset.
[106] For subsequent set terminals S of flip-flops F3 to Fn-2, analog switches AS3 to ASn-2 are turned on when the switching signal LRO is at a high level, and flip-flop F2 preceding to the set terminal S is turned on. In the case of providing the output of ˜Fn-3, and at the low level, the signal is turned off. On the other hand, the analog switches BS3 to BSn-2 are turned off when the switching signal LRO is at the high level. It is turned on to provide the set terminal S with the outputs of the flip-flops F4 to Fn-1 of the blocking.
[107] In addition, with respect to the reset terminal R of the flip-flops F3 to Fn-2, the analog switches AR3 to ARn-2 are turned on when the switching signal LRO is at a high level, and the cut-off flips to the reset terminal R. -Provides outputs of flops F4 to Fn-1, which are in the OFF state when the level is low, while analog switches BR3 to BRn-2 are in the OFF state when the switching signal LRO is at the high level. Is turned on to provide the reset terminal R with an output at the output terminal Q of the flip-flops F2 to Fn-3 in the preceding stage.
[108] Next, for the set terminal S of the flip-flop Fn-1 to be cut off, the analog switch ASn-1 is turned on when the switching signal LRO is at a high level, and the flip-flop Fn-2 preceding the set terminal S is turned on. Output is supplied, and when the low level is turned off, the analog switch BSn-1 is turned off when the switching signal LRO is at a high level, and is turned on when the switching signal LRO is at a high level. The start pulse SPO is provided to terminal S.
[109] In addition, with respect to the reset terminal R of the flip-flop Fn-1, the analog switch ARn-1 is turned ON when the switching signal LRO is at a high level, so that the reset terminal R of the flip-flop Fn is turned off. Provides an output, and when the level is low, the signal is turned off. On the other hand, the analog switch BRn-1 is turned off when the switching signal LRO is at a high level, and is turned on when the level is low. Provide terminal R with the output of the flip-flop Fn-2 in front.
[110] Furthermore, with respect to the set terminal S of the last flip-flop Fn, the analog switch ASn is turned ON when the switching signal LRO is at a high level, and outputs the output of the flip-flop Fn-1 of the previous stage to the set terminal S. If the low level is provided, the signal is turned off, and the analog switch BSn is turned off when the switching signal LRO is at a high level, and is turned on at the low level, and the set terminal S is grounded. .
[111] In addition, with respect to the reset terminal R of the flip-flop Fn, the analog switch ARn is turned on when the switching signal LRO is at a high level, provides an output of its own terminal, and resets it when it is at a low level. On the other hand, the analog switch BRn is turned off when the switching signal LRO is at a high level, and is turned on when the switching signal LRO is at a low level, thereby providing a high level driving voltage Vcc to the reset terminal R.
[112] Accordingly, these analog switches AS1 to ASn, AR1 to ARn, and analog switches BS1 to BSn and BR1 to BRn are controlled in opposition by the switching signal LRO, so that flip-flop F2 is ultra-short, flip-flop Fn as described above. This final stage is synchronized with the clock signal CK. As described above, the start pulse SPO is sequentially shifted with the flip-flops F2, F3, F4, ..., Fn, and the output signals S2, S3, ... In the case of outputting in the order, and the flip-flop Fn-1 is the first stage, the flip-flop F1 is the final stage, and the start pulse SPO is sequentially the flip-flop Fn-1, Fn-2, Fn-3, ... , Fn is shifted, and the bidirectional shift operation when the output signals Sn-1, Sn-2, ... are output in the order of S1 can be realized.
[113] The set level S of the flip-flops F1 and Fn is not necessarily input to the ground level, but may be a voltage level at which the flip-flops F1 and Fn are not set. Similarly, the reset terminal R is not limited to the drive voltage Vcc, but may be a voltage level at which the flip-flops F1 and Fn are reset.
[114] In the shift register 51 configured as described above, it should be noted that in response to the output signals of the flip-flop (F2 and Fn-1 in the present shift register 51) at the start of the shift operation, An operation control circuit 54 for disabling the level shifter 13 and outputting an enable signal ENB for activating the level shifter 13 in response to output signals of the flip-flops Fn and F1 at the final stage. Is doing. The switching signal LRO is input to the operation control circuit 54 to control the output of the enable signal ENB in accordance with the shift direction. That is, when the flip-flop of the start end of the shift operation is F2, the level shifter 13 is deactivated in response to the output signal S2 of the flip-flop F2, and the output of the flip-flop Fn of the last end is output. The level shifter 13 is activated in response to the signal Sn. If the flip-flop at the start end is Fn-1, the level shifter 13 is activated in response to the output signal Sn-1 of the flip-flop Fn-1. The shifter 13 is deactivated, and the level shifter 13 is activated in response to the output signal S1 of the flip-flop F1 at the final stage.
[115] Fig. 16 shows the analog switches AS and AR; It is a block diagram which shows one structural example of BS and BR. These analog switches AS, AR; BS and BR are composed of a pair of NMOS transistors Nsw and PMOS transistors Psw and an inverter INVsw. The switching signal LRO or the switching signal LROB inverted from the inverter INV1r is provided directly to the gate of the NMOS transistor Nsw, and inverted from the inverter INVsw and then provided to the gate of the PM0S transistor Psw. Therefore, when the switching signals LRO and LROB are at the high level, both transistors Nsw and Psw are turned on together, and are output as the output signal OUT by passing the input signal IN of positive polarity. On the other hand, when the switching signals LRO and LROB are at the low level, both transistors Nsw and Psw are turned off together, the input signal IN is blocked, and the output signal OUT is not output. At this time, since the switching signal LRO is input to the analog switches AS and AR, and the inverted switching signal LROB is input to the analog switches BS and BR, the reverse operation is performed as described above.
[116] Fig. 17 is a waveform diagram for explaining the operation of the shift register 51 configured as described above. When the switching signal LR is at the high level, the analog switches AS and AR are turned ON, and the analog switches BS and BR are turned OFF by the switching signal LRO after boosting at the same polarity. Therefore, the start pulse SPO in which the start pulse SP is boosted by the level shifter 13 is input to the set terminal S of the flip-flop F2 of the second stage. Specifically, in the state where the start pulse SPO is active at the high level, the flip-flop F2 is set at the timing of rising of the clock signal CK, and the output signal S2 is output from the output terminal Q of the flip-flop F2.
[117] The output signal S2 is input to the set terminal S of the flip-flop F3 of the cutoff, and the flip-flop F3 is set at the rising timing of the clock signal CKB, that is, the falling timing of the clock signal CK, and the output signal at the output terminal Q. S3 is output. The output signal S3 is input to the set terminal S of the flip-flop F4 of the interruption in the same manner, and to the reset terminal R of the flip-flop F2 of the front end to reset the operation of the flip-flop F2, The output signal S2 is made low level inactive.
[118] After that, the output signals S 4 to Sn-1 are outputted at the output terminals Q of the flip-flops F4 to Fn-1, respectively, and are respectively input to the set terminals S of the flip-flops F5 to Fn of the cutoff, respectively. Is input to the reset terminal R of the flip-flops F3 to Fn-2. At the output terminal Q of the flip-flop Fn, the output signal Sn is output, and is input to the reset terminal R of the flip-flop Fn-1 at the front end and to the reset terminal R of the terminal.
[119] As described above, as shown on the left side of Fig. 17, when the switching signal LR is at a high level, the flip-flop F2 to which the start pulse SPO is input is set as the start end of the shift operation, to the last flip-flop Fn. The output signals S2 to Sn are output without performing the shift operation sequentially every half cycle of the clock signal CK. At this time, the output signal Sn of the final stage is reset at the output of the magnetic terminal immediately after outputting from the magnetic terminal. In addition, since the flip-flop F1 does not participate in the shift operation when the switching signal LR is high level as described above, and is always reset, the output signal S1 remains low level.
[120] On the other hand, as shown in the right side of Fig. 17, when the switching signal LR is at the low level, the analog switch AS and AR are turned off by the switching signal LRO after boosting with the same polarity, and the analog switch BS, BR turns on. Therefore, the start pulse SPO in which the start pulse SP is boosted by the level shifter 13 is input to the set terminal S of the flip-flop Fn-1 of the n-th stage. Detailed descriptions of the operations of the flip-flops Fn-2 to F1 will be omitted. However, the flip-flop Fn-1 is used as the start end of the shift operation, and the shift operation is not performed sequentially to the last flip-flop F1. Instead, the output signals Sn-1 to S1 are sequentially output for every half period of the clock signal CK. At this time, the output signal S1 of the last stage is reset immediately after the output as described above. In addition, since the flip-flop Fn does not participate in the shift operation when this switching signal LR is low level and is always reset, the output signal Sn remains low level.
[121] Therefore, as described above, the output signals S2 to Sn-1 are valid as the output of the shift register 51, but the operation control of the level shifter 13 by the operation control circuit 54 described later is described above. As mentioned, the output signal Sn or S1 of the last stage is used. In this case, as shown in Fig. 17, when the switching signal LR is at a high level, the enable signal ENB is inactive at the time when the output signal S2 of the flip-flop F2 at the start of the shift operation is output. It becomes a high level and becomes an active low level when the output signal Sn of the last flip-flop Fn is output. In contrast, when the switching signal LR is at the low level, the enable signal ENB is at an inactive high level when the output signal Sn-1 of the flip-flop Fn-1 at the start of the shift operation is output. When the output signal S1 of the flip-flop F1 of the last stage is outputted, it becomes an active low level. 18 is a block diagram showing an example of the configuration of the operation control circuit 54. As shown in FIG. The operation control circuit 54 includes the analog switches AS and AR in a set reset flip-flop made up of two inverted logic circuits NOR1 and NOR2 of the CMOS configuration. BS, BR, and analog switches A1 and A2 of the same configuration; It is comprised including B1, B2, and inverter INVct1.
[122] The analog switches A1 and A2 do not perform the same operations as the analog switches AS and AR, and are turned on when the switching signal LRO is at a high level, and are turned off when at a low level. On the other hand, since the switching signals LRO are provided inverted by the inverter INVct1, the analog switches B1 and B2 do not perform the same operations as the analog switches BS and BR, and when the switching signals LRO are at a low level, they are turned ON. In the high level, the signal is turned off.
[123] In this operation control circuit 54, instead of the output signal S1 of the operation control circuit 14 shown in Fig. 4, an output signal S2 or Sn-1 is input to one input of the inversion logic circuit NOR1, and the inversion is performed. The output signal Sn or S1 is input to one input of the logic sum circuit NOR2.
[124] When the switching signal LRO is at a high level, the output signal S2 is input to one input of the inversion logic circuit NOR1 through the analog switch A1, and the output signal Sn is inverted through the analog switch A2. It is input to one input of logic sum circuit NOR2. As described above, the outputs of the other inverted logic circuits NOR2 and NOR1 are input to the other inputs of the inverted logic circuits NOR1 and NOR2.
[125] Therefore, the enable signal ENB, which is the output of the inversion logic circuit NOR2, has a low level at the time when the output signal S2 is output as described above, that is, the output of the inversion logic circuit NOR1, that is, the other input of the inversion logic circuit NOR2, is low. Since the output signal Sn is at the low level, the output signal Sn is at the inactive high level. Thereafter, even if the output signal S2 goes low, the output of the inversion logic circuit NOR1 is at a low level due to the high level output of the inversion logic circuit NOR2, that is, the output of the inversion logic circuit NOR2, that is, the enable signal ENB Maintain high level.
[126] After that, when the output signal Sn is outputted, the enable signal ENB, which is the output of the inversion logic circuit NOR2, becomes an active low level, whereby the two inputs of the inversion logic circuit NOR1 are brought low together, thereby inverting the logic circuit NOR1. Output goes high. After that, even when the output signal Sn becomes low, the output of the inversion logic circuit NOR2, that is, the enable signal ENB, is output until the output signal S2 is output again by the high level output of the inversion logic circuit NOR1. It is kept at the low level.
[127] In contrast, when the switching signal LRO is at a low level, the output signal Sn-1 is input to one input of the inversion logic circuit NOR1 through the analog switch B1, and the output signal S1 is connected to the analog switch B2. It is input to one input of the inversion logic circuit NOR2.
[128] Therefore, the enable signal ENB, which is the output of the inversion logic circuit NOR2, has a low level at the time when the output signal Sn-1 is output as described above, that is, the output of the inversion logic circuit NOR1, that is, the other input of the inversion logic circuit NOR2 is low level. Since the output signal S1 is at a low level, the output signal S1 is at an inactive high level. Thereafter, even when the output signal Sn-1 goes low, the output of the inversion logic circuit NOR1 is low level due to the high level output of the inversion logic circuit NOR2, that is, the output of the inversion logic circuit NOR2, that is, the enable signal ENB. Is maintained at a high level.
[129] After that, when the output signal S1 is outputted, the enable signal ENB, which is the output of the inversion logic circuit NOR2, becomes an active low level, whereby the two inputs of the inversion logic circuit NOR1 are brought low together, whereby the inversion logic circuit The output of NOR1 goes high. After that, even if the output signal S1 goes low, the output of the inversion logic circuit NOR2, that is, the enable signal ENB, is output again by the high level output of the inversion logic circuit NOR1. Until it is at a low level.
[130] In this way, the operation of the level shifter 13 can also be controlled with respect to the bidirectional shift operation. In recent years, as shown by the monitor panel of a video camera or a digital camera, the apparatus which can display the mirror image which inverted the upper and left and right of a display image according to the direction of an image display part is put into practical use, and inverts a display image in this way. By using the bidirectional shift register 51 capable of switching the shift direction of data as a shift register of a possible display device, the mirror image display is possible only by switching the shift direction, thereby storing a video signal. The means can be omitted.
[131] In this case, in the image display apparatus 21 shown in Fig. 6, the switching signal LR is further inputted from the control circuit 23 for generating the video signal DAT to the shift register 26a, thereby inverting the left and right. The image can be displayed. Further, by further inputting the same switching signal UD from the control circuit 23 to the shift register 25a, it is possible to display upside down images.
[132] Another embodiment according to the present invention will be described with reference to FIGS. 19 to 21 as follows.
[133] Fig. 19 is a block diagram showing the electrical configuration of the shift register 61 of still another embodiment according to the present invention. The shift register 61 is similar to the shift register 51, and the corresponding parts are added with the same reference numeral or the subscript a in the same reference numeral, and description thereof will be omitted. It should be noted that in this shift register 61, the first stage flip-flop circuit to which the start pulse SPO is input in the shift register section 62 is H3a where the third stage, that is, s = 3, In addition to Hn-2a, when each flip-flop circuit, for example, H5a, outputs an output signal S5, the shift register 51 resets the flip-flop circuit H4a of the previous stage. At 61, the flip-flop circuit H3a at the front end is reset.
[134] Therefore, the operation control circuit 54 is configured in the same manner and performs the same operation. However, in Fig. 18, the output signals inputted to the analog switches A1 and B1 are S3, Sn-1, S3, Sn. Is changed to -2.
[135] 20 is a block diagram showing an example of a configuration of the shift register section 62 in detail. In the parts corresponding to the configuration in Fig. 15, the same reference numeral or the same reference numeral is added to the subscript a. In the shift register section 62, the configuration regarding the flip-flops F1 and Fn is the same as that of the shift register section 52. The configuration regarding the remaining flip-flops F2 to Fn-1 is the shift register section 52. Is different from
[136] That is, the flip-flop F2 is configured in the same manner as the flip-flop F1, and with respect to the set terminal S of the flip-flop F2, the analog switch AS2 is turned on when the switching signal LRO is at a high level. The terminal S is grounded and is turned OFF when it is at a low level. On the other hand, the analog switch BS2 is turned OFF when the switching signal LRO is at a high level, and is turned on when it is at a low level. Is connected to the output terminal Q of the flip-flop F3 of the cutoff.
[137] In addition, with respect to the reset terminal R of the flip-flop F2, the analog switch AR2 is turned on when the switching signal LRO is at a high level to provide a high level driving voltage Vcc to the reset terminal R, Level, it is in the OFF state. On the other hand, the analog switch BR2 is in the OFF state when the switching signal LRO is at the high level, and is in the ON state when the switching signal LRO is at the low level, and is flip-flop in front of the reset terminal R. Provide the output of F1 and reset it.
[138] With respect to the set terminal S of the flip-flop F3 of the interruption, the analog switch AS3 is turned on when the switching signal LRO is at a high level, and provides the start pulse SPO to the set terminal S, and is turned off when at a low level. On the other hand, the analog switch BS3 is turned off when the switching signal LRO is at high level, and is turned on when the switching signal LRO is at high level, and the set terminal S is connected to the output terminal Q of the flip-flop F4. Connect.
[139] In addition, with respect to the reset terminal R of the flip-flop F3, the analog switch AR3 is turned ON when the switching signal LRO is at the high level, and the output terminal Q of the flip-flop F5 of the next interruption to the reset terminal R is turned on. Provides an output at &lt; RTI ID = 0.0 &gt; and &lt; / RTI &gt; goes low when it is at low level, whereas analog switch BR3 is turned off when the switching signal LRO is at high level, and is turned on when it is at low level and reset. The terminal R is provided with the output at the output terminal Q of the flip-flop F1 of the preceding stage and reset.
[140] For the next set terminal S of flip-flops F4 to Fn-3, the analog switches AS4 to ASn-3 are turned on when the switching signal LRO is at a high level, and the flip-flop of the previous stage is set to the set terminal S. When the output of F3 to Fn-4 is provided and is at a low level, it is turned off. On the other hand, the analog switches BS4 to BSn-3 are turned off when the switching signal LRO is at a high level. In the ON state, the set terminal S is provided with the outputs of the flip-flops F5 to Fn-2 of the blocking.
[141] In addition, with respect to the reset terminal R of the flip-flops F4 to Fn-3, the analog switches AR4 to ARn-3 are turned on when the switching signal LRO is at a high level, and the reset terminal R is connected to the reset terminal R. The output of flip-flop F6 to Fn-1 is provided, and when it is at the low level, it is turned off, whereas analog switches BR4 to BRn-3 are turned off when the switching signal LRO is at a high level and low In the case of the level, the signal is turned on to provide the reset terminal R with the output at the output terminal Q of the flip-flops F2 to Fn-5 of the previous stage.
[142] In addition, with respect to the set terminal S of the disconnected flip-flop Fn-2, the analog switch ASn-2 is turned ON when the switching signal LRO is at a high level, and the flip-flop Fn-3 preceding the set terminal S is turned on. Output at the low level, the signal is turned off, and the analog switch BSn-2 is turned off when the switching signal LRO is at a high level, and turned on when the switching signal LRO is at a high level. The start pulse SPO is provided to terminal S.
[143] Further, with respect to the reset terminal R of the flip-flop Fn-2, the analog switch ARn-2 is turned ON when the switching signal LRO is at a high level, and the flip-flop Fn of the next blocking is applied to the reset terminal R. Output at the low level, the signal is turned off, and the analog switch BRn-2 is turned off when the switching signal LRO is at a high level, and turned on when the switching signal LRO is at a high level. The set terminal R provides the output of the flip-flop Fn-4 of the preceding stage.
[144] In addition, the flip-flop Fn-1 of blocking is comprised like the flip-flop Fn of the last stage, and with respect to the set terminal S, the analog switch ASn-1 turns ON when the said switching signal LRO is high level. An output of the flip-flop Fn-2 of the front end is provided to the set terminal S, and when it is at the low level, it is turned off, while the analog switch BSn-1 is turned off when the switching signal LRO is at a high level. When the level is low, the set terminal S is grounded.
[145] In addition, with respect to the reset terminal R of the flip-flop Fn-1, the analog switch ARn-1 is turned ON when the switching signal LRO is at a high level to provide the output of the cut-off flip-flop Fn, and low. Level, the signal is turned off. On the other hand, the analog switch BRn-1 is turned off when the switching signal LRO is at a high level, and turned on when the switching signal LRO is at a high level. Provide the driving voltage Vcc.
[146] Therefore, these analog switches AS1 to ASn, AR1 to ARn, and analog switches BS1 to BSn and BR1 to BRn are controlled halfway by the switching signal LRO, so that flip-flop F3 is ultra-short, flip-flop Fn as described above. At this final stage, as shown in Fig. 21, in synchronization with the clock signal CK, the start pulse SPO is sequentially shifted to the flip-flops F3, F4, F5, ..., Fn, and output signals S3, S4, When outputted in the order of Sn, flip-flop Fn-2 is the first stage, flip-flop F1 is the last stage, and start pulse SPO is sequentially flip-flop Fn-2, Fn-3, Fn- 4, ... The bidirectional shift operation in the case of shifting with F1 and outputting in the order of output signals Sn-2, Sn-3, ... S1 can be realized.
[147] In addition, since it is reset to the output signal of the preceding or blocking flip-flop, the pulse width of the output signals S3 to Sn-2 is equal to one cycle of the clock signal CK, and therefore, as shown in FIG. You can do it by boat. The pulse width is not limited to the above two times but may be three times or more depending on the time required for writing the video signal DAT to the pixel PIX.
[148] On the other hand, when the switching signal LR is at the high level, the output signals S1 and S2 are kept at the low level because the flip-flops F1 and F2 are reset, and the output signals Sn-1 and Sn are Since the flip-flops Fn-1 and Fn are reset by the output signal Sn, the output pulse waveform is different from the others. Similarly, when the switching signal LR is at the low level, the output signals Sn and Sn-1 are kept at the low level, and the output signals S2 and S1 are different from other pulse waveforms.
[149] Another embodiment of the present invention will be described with reference to FIG. 22 as follows.
[150] Fig. 22 is a block diagram showing the electrical configuration of the shift register 71 of another embodiment according to the present invention. The shift register 71 is similar to the shift registers 31 and 51, and the same reference numerals are given to corresponding parts, and description thereof will be omitted. It should be noted that in the shift register 71, when the operation control circuit 54 deactivates the level shifter 13 in response to the enable signal ENB, the shift of the level shifter 13a is performed. In the input of the input switching element, the input control circuit 32 is provided with a signal of a level at which the input switching element blocks.
[151] Therefore, the deactivation of the current-driven level shifter 13 can be realized and the current of the NMOS transistor N2, which is an input switching element, can be reduced at the time of deactivation.
[152] Another embodiment according to the present invention will be described with reference to FIG. 23 as follows.
[153] Fig. 23 is a block diagram showing the electrical configuration of the shift register 81 of still another embodiment according to the present invention. This shift register 81 is similar to the shift registers 41 and 51. Therefore, the shift register 81 includes the input control circuit 32 and, when the operation control circuit 54 deactivates the level shifter 13 in response to the enable signal ENB. And an output stabilization circuit 42 which maintains the output voltage of the level shift section l3a at a predetermined value.
[154] Therefore, while the level shifter 13 is stopped, the output voltage of the level shifter 13 is maintained at a predetermined value, and malfunctions of the flip-flops F2 and Fn-1 can be prevented, resulting in more stable operation. The shift register can be realized.
[155] Further, in the shift registers 71 and 81, instead of the shift register portion 52, the shift register portion 62 of the shift register 61, or another shift register portion of s = 4 or more may be used. Of course.
[156] In the above description, the image display device 21 is taken as an example of application of the shift registers 11, 31, 41, 51, 61, 71, 81. However, the shift registers 11, 31, 41, 51, 61 are used. It can be widely applied as long as an input signal having an amplitude lower than the driving voltage Vcc of 71, 81 is provided. However, as the image display device 21 is strongly requested to improve the resolution and increase the display area, the shift registers 11, 31, 41, 51, 61, 71, 81 have a large number of stage shifters. It is particularly effective because the driving capability of (13) cannot be sufficiently secured.
[157] In the detailed description of the invention, the specific embodiments or embodiments disclosed are for the purpose of clearly signing the technical contents of the present invention, and should not be construed as limited to such specific embodiments. Various modifications can be made without departing from the scope of the invention as defined by the spirit of the invention and the scope of the following claims.
[158] According to the present invention, even when the input signal is made small in order to reduce the power consumption, the shift register can operate normally by the level shifter and at the same time reduce the power consumption in the level shifter, and using the same. A display device can be obtained.

权利要求:
Claims (21)
[1" claim-type="Currently amended] In the shift register for sequentially transmitting a signal of a plurality of flip-flops input,
A level shifter for boosting the input signal having an amplitude lower than the driving voltage of the flip-flop and applying it to the first flip-flop;
In response to the output of the flip-flop of any x-th stage and the flip-flop of any y-th stage (where x <y), the level shifter if the x-th stage flip-flop transmits the input signal. And operation control means for activating the signal and activating the level shifter when the y-th flip-flop transmits the input signal.
[2" claim-type="Currently amended] The shift register according to claim 1, wherein the x-th stage is the first stage and the y-th stage is the last stage.
[3" claim-type="Currently amended] 2. The shift register according to claim 1, wherein said level shifter has a current shift type level shift portion which is always connected to an input switching element provided with said input signal during operation.
[4" claim-type="Currently amended] 4. The signal according to claim 3, wherein, when said operation control means deactivates said level shifter, with respect to said operation control means, a signal of a level at which said input switching element interrupts an input of said input switching element of said level shift portion. Shift register further comprising an input control means for providing a.
[5" claim-type="Currently amended] The shift register according to claim 1, wherein the level shifter includes an output stabilizer that maintains an output voltage at a predetermined value in the case of the deactivation.
[6" claim-type="Currently amended] A shift register capable of sequentially transmitting a signal input from a plurality of flip-flops and switching a shift direction,
A level shifter for boosting the input signal having an amplitude lower than the driving voltage of the flip-flop and applying the flip-flop to any s-th stage; and
In response to the output of the flip-flop of any x-th stage (where s ≤ x) and the flip-flop of any y-th stage (where x <y), the flip-flop of the x-th stage is the input. And motion control means for disabling the level shifter when transmitting a signal, and activating the level shifter when the y-th flip-flop transmits the input signal.
[7" claim-type="Currently amended] 7. The shift register according to claim 6, wherein the x th stage is the s th stage and the y th stage is the last stage.
[8" claim-type="Currently amended] 7. The shift register according to claim 6, wherein said level shifter has a current shift type level shift portion which, during operation, always conducts an input switching element provided with said input signal.
[9" claim-type="Currently amended] The signal of a level according to claim 8, wherein, when said operation control means deactivates said level shifter with respect to said operation control means, a signal of a level at which said input switching element cuts off at the input of said input switching element of said level shift portion. The shift register further comprises an input control means for providing a.
[10" claim-type="Currently amended] 7. The shift register according to claim 6, wherein the level shifter includes an output stabilizer that maintains an output voltage at a predetermined value in the case of the deactivation.
[11" claim-type="Currently amended] A plurality of scan signal lines and data signal lines which cross each other, and
A scan signal line driver circuit and a data signal line driver circuit for displaying an image by writing an image signal through the scan signal line and the data signal line, respectively, in each pixel region formed by being divided by the scan signal line and the data signal line;
At least one of the scan signal line driver circuit and the data signal line driver circuit includes a shift register which is formed integrally with the display panel and sequentially transmits a signal input with a plurality of stages of flip-flops,
The shift register is a level shifter for boosting the input signal having an amplitude lower than the driving voltage of the flip-flop and applying it to a flip-flop at the first stage, and a flip-flop at any x-th stage and any y-th stage. In response to the output of the flip-flop (x <y), if the flip-flop of the x-th stage transmits the input signal, the level shifter is disabled, and the flip-flop of the y-th stage is And an operation control means for activating the level shifter when an input signal is transmitted.
[12" claim-type="Currently amended] A plurality of scan signal lines and data signal lines which cross each other, and
A scan signal line driver circuit and a data signal line driver circuit for displaying an image by writing an image signal through the scan signal line and the data signal line, respectively, in each pixel region formed by being divided by the scan signal line and the data signal line;
At least one of the scan signal line driver circuit and the data signal line driver circuit is formed integrally with the display panel, and is capable of sequentially transferring signals inputted by a plurality of flip-flops and simultaneously switching a shift direction. And
The shift register boosts the input signal having an amplitude lower than the driving voltage of the flip-flop and applies it to a flip-flop of any s-th stage, and an arbitrary x-th stage (where s ≤ x In response to the flip-flop of < RTI ID = 0.0 &gt;) &lt; / RTI &gt; and a flip-flop of any y th stage (where x &lt; y), if the x th stage flip-flop transmits the input signal, the level shifter is disabled. And operation control means for activating the level shifter when the y-th flip-flop transmits the input signal.
[13" claim-type="Currently amended] A level shifter for converting and outputting the voltage amplitude of the input signal;
A plurality of flip-flops for sequentially transmitting the output signal of the level shifter from a predetermined stage, and
And an operation control circuit for switching deactivation and activation of the level shifter based on an output of each of two predetermined flip-flops of the plurality of flip-flops.
[14" claim-type="Currently amended] 15. The shift register according to claim 13, wherein the two predetermined flip-flops are stages for sequentially starting and terminating the output signals of the level shifter.
[15" claim-type="Currently amended] A level shifter for converting and outputting the voltage amplitude of the input signal;
A plurality of flip-flops for sequentially transmitting the output signal of the level shifter, and
The level shifter if the flip-flop of the x-th stage transmits the signal based on the output of each of the flip-flops of the x-th and y-th stages (where x <y) among the plurality of flip-flops. And an operation control circuit for activating the signal and activating the level shifter when the y-th flip-flop transmits the signal.
[16" claim-type="Currently amended] The shift register according to claim 15, wherein the x-th stage and the y-th stage are stages for sequentially starting and terminating the output signals of the level shifter, respectively.
[17" claim-type="Currently amended] A level shifter for converting and outputting the voltage amplitude of the input signal;
It is possible to sequentially transmit the output signal of the level shifter, and includes a plurality of flip-flops for switching the shift direction,
The output signal of the level shifter is applied to the flip-flop of the s-th stage in the shift direction among the flip-flops of the plurality of stages,
Of the flip-flops of the plurality of stages, the flip-flop of the x-th stage is based on the output of each of the flip-flops of the x-th and y-th stages (s ≤ x <y) in the shift direction. And an operation control circuit for disabling the level shifter when transmitting an input signal and activating the level shifter when the y-th flip-flop transmits the input signal.
[18" claim-type="Currently amended] 18. The shift register according to claim 17, wherein the x th stage is the s th stage and the y th stage is the last stage.
[19" claim-type="Currently amended] A plurality of scan signal lines and data signal lines which cross each other, and
A scan signal line driver circuit and a data signal line driver circuit for displaying an image by writing an image signal through the scan signal line and the data signal line, respectively, in each pixel region formed by being divided by the scan signal line and the data signal line;
A shift register included in at least one of the scan signal line driver circuit and the data signal line driver circuit,
A level shifter for converting and outputting the voltage amplitude of the input signal;
A plurality of flip-flops for sequentially transmitting the output signal of the level shifter from a predetermined stage, and
And a shift register including an operation control circuit for switching the deactivation and activation states of the level shifter based on an output of each of two predetermined flip-flops of the plurality of flip-flops.
[20" claim-type="Currently amended] A plurality of scan signal lines and data signal lines which cross each other, and
A scan signal line driver circuit and a data signal line driver circuit for displaying an image by writing an image signal through the scan signal line and the data signal line, respectively, in each pixel region formed by being divided by the scan signal line and the data signal line;
A shift register included in at least one of the scan signal line driver circuit and the data signal line driver circuit,
A level shifter for converting and outputting the voltage amplitude of the input signal;
A plurality of flip-flops for sequentially transmitting the output signal of the level shifter, and
The level shifter if the flip-flop of the x-th stage transmits the signal based on the output of each of the flip-flops of the x-th and y-th stages (where x <y) among the plurality of flip-flops. And a shift register including an operation control circuit to activate the level shifter when the y-th flip-flop transmits the signal.
[21" claim-type="Currently amended] A plurality of scan signal lines and data signal lines which cross each other, and
A scan signal line driver circuit and a data signal line driver circuit for displaying an image by writing an image signal through the scan signal line and the data signal line, respectively, in each pixel region formed by being divided by the scan signal line and the data signal line;
A shift register included in at least one of the scan signal line driver circuit and the data signal line driver circuit,
A level shifter for converting and outputting the voltage amplitude of the input signal;
It is possible to sequentially transmit the output signal of the level shifter, and comprises a plurality of flip-flops capable of switching the shift direction,
The output signal of the level shifter is applied to the flip-flop of the s-th stage in the shift direction among the flip-flops of the plurality of stages,
Of the flip-flops of the plurality of stages, the flip-flop of the x-th stage is based on the output of each of the flip-flops of the x-th and y-th stages (where s ≤ x y y) in the shift direction. And a shift control circuit for disabling the level shifter when transmitting an input signal and activating the level shifter when the flip-flop of the y th stage transmits the input signal.

类似技术:

---

公开号 | 公开日 | 专利标题

---

US8942339B2|2015-01-27|Shift register

---

US10643563B2|2020-05-05|Display device

---

US9747854B2|2017-08-29|Shift register, gate driving circuit, method for driving display panel and display device

---

US9799287B2|2017-10-24|Shift register unit and driving method thereof, gate driving circuit and display device

---

US9305509B2|2016-04-05|Shift register unit, gate driving circuit and display apparatus

---

US8493312B2|2013-07-23|Shift register

---

RU2543312C2|2015-02-27|Shift register, scanning signal line drive circuit, display device having same

---

US8031827B2|2011-10-04|Shift register

---

JP5128102B2|2013-01-23|Shift register circuit and image display apparatus including the same

---

JP4593071B2|2010-12-08|Shift register and display device having the same

---

KR100616789B1|2006-08-28|Drive circuit of display apparatus

---

US8614661B2|2013-12-24|Shift register unit, gate driving device and liquid crystal display

---

KR101170241B1|2012-07-31|Driving circuit for electric paper display and display device

---

JP4782191B2|2011-09-28|Display device and driving method thereof

---

US8223112B2|2012-07-17|Shift register receiving all-on signal and display device

---

US7233308B2|2007-06-19|Shift register

---

US8165262B2|2012-04-24|Shift register of a display device

---

US8531376B2|2013-09-10|Bootstrap circuit, and shift register, scanning circuit, display device using the same

---

KR101340197B1|2013-12-10|Shift register and Gate Driving Circuit Using the Same

---

JP5173618B2|2013-04-03|Shift register, driving method thereof, and driving device for liquid crystal display panel

---

JP5372268B2|2013-12-18|Scanning signal line driving circuit, display device including the same, and scanning signal line driving method

---

JP4990034B2|2012-08-01|Shift register circuit and image display apparatus including the same

---

US20190156778A1|2019-05-23|Shift register unit, gate driving circuit, and driving method

---

KR100595797B1|2006-06-30|Bidirectional shift register shifting pulse in both forward and backward directions

---

CN100397444C|2008-06-25|Image display apparatus having plurality of pixels arranged in rows and columns

同族专利:

---

公开号 | 公开日

---

CN1447298A|2003-10-08|

---

TW200402680A|2004-02-16|

---

CN100399380C|2008-07-02|

---

US20030179174A1|2003-09-25|

---

JP4480944B2|2010-06-16|

---

US7190342B2|2007-03-13|

---

KR100523509B1|2005-10-25|

---

TWI290706B|2007-12-01|

---

JP2004005904A|2004-01-08|

引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

法律状态:
2002-03-25|Priority to JPJP-P-2002-00084302

---

2002-03-25|Priority to JP2002084302

---

2003-01-09|Priority to JPJP-P-2003-00003284

---

2003-01-09|Priority to JP2003003284A

---

2003-03-25|Application filed by 샤프 가부시키가이샤

---

2003-10-01|Publication of KR20030077427A

---

2005-10-25|Application granted

---

2005-10-25|Publication of KR100523509B1

优先权:

---

申请号 | 申请日 | 专利标题

---

JPJP-P-2002-00084302|2002-03-25|

---

JP2002084302|2002-03-25|

---

JPJP-P-2003-00003284|2003-01-09|

---

JP2003003284A|JP4480944B2|2002-03-25|2003-01-09|Shift register and display device using the same|